Thesis presentation: «Dynamically reconfigurable architecture for embedded Computer Vision systems»

This work presents a new hardware architecture to accelerate computer vision applications in embedded systems. The proposed architecture exploits both spatial and temporal parallel computing paradigms, executing data parallel operations in SIMD mode, task parallel operations in MIMD mode and deriving the execution of high level operations to a sequential processor.

The computing paradigm can switched at runtime according to the requirements of the application. This architecture was prototyped in an FPGA and validated by means of the implementation of a wide range of algorithms and usual operations in image processing. This proposal permits to implement a single chip device which is able to execute most of Computer vision algorithms.

The thesis opts to the international PhD.