CMOS SPDT Switch Topologies in the Frequency Range of 6 to 20 GHz

This work builds on a recent contribution from the literature to improve isolation on single-pole single-throw switches by introducing an additional transistor at the gate of the series devices in a series–shunt architecture implemented in an FDSOI process. This paper explores the effects of this extra transistor when used in single-pole double-throw switches implemented with RF CMOS transistors in a 130 nm SiGe technology over the 6-20 GHz range. The insights drawn from the post-layout simulations confirm improved isolation, albeit at the cost of higher area consumption, lower output power handling, and higher insertion loss. The overall performance is evaluated using a figure of merit that combines these parameters, showing that the series–shunt configuration offers the best trade-off, while the analyzed approach may be advantageous in applications with area-constrained designs or very high isolation requirements.

Palabras clave: Switch, CMOS, single-pole double-throw, SPDT, RF, radiofrequency