A multi-method simulation toolbox to study performance and variability of nanowire FETs
© 2019 by the authors. An in-house-built three-dimensional multi-method semi-classical/classical toolbox has been developed to characterise the performance, scalability, and variability of state-of-the-art semiconductor devices. To demonstrate capabilities of the toolbox, a 10 nm gate length Si gate-all-around field-effect transistor is selected as a benchmark device. The device exhibits an off-current (IOFF) of 0.03 μA/μm, and an on-current (ION) of 1770 μA/μm, with the ION/IOFF ratio 6.63×104, a value 27% larger than that of a 10.7 nm gate length Si FinFET. The device SS is 71 mV/dec, no far from the ideal limit of 60 mV/dec. The threshold voltage standard deviation due to statistical combination of four sources of variability (line- and gate-edge roughness, metal grain granularity, and random dopants) is 55.5 mV, a value noticeably larger than that of the equivalent FinFET (30 mV). Finally, using a fluctuation sensitivity map, we establish which regions of the device are the most sensitive to the line-edge roughness and the metal grain granularity variability effects. The on-current of the device is strongly affected by any line-edge roughness taking place near the source-gate junction or by metal grains localised between the middle of the gate and the proximity of the gate-source junction.
keywords: Drift-diffusion, Monte Carlo, Nanowire field-effect transistors, Schrödinger based quantum corrections, Variability effects
Publication: Article
1624014957540
June 18, 2021
/research/publications/a-multi-method-simulation-toolbox-to-study-performance-and-variability-of-nanowire-fets
© 2019 by the authors. An in-house-built three-dimensional multi-method semi-classical/classical toolbox has been developed to characterise the performance, scalability, and variability of state-of-the-art semiconductor devices. To demonstrate capabilities of the toolbox, a 10 nm gate length Si gate-all-around field-effect transistor is selected as a benchmark device. The device exhibits an off-current (IOFF) of 0.03 μA/μm, and an on-current (ION) of 1770 μA/μm, with the ION/IOFF ratio 6.63×104, a value 27% larger than that of a 10.7 nm gate length Si FinFET. The device SS is 71 mV/dec, no far from the ideal limit of 60 mV/dec. The threshold voltage standard deviation due to statistical combination of four sources of variability (line- and gate-edge roughness, metal grain granularity, and random dopants) is 55.5 mV, a value noticeably larger than that of the equivalent FinFET (30 mV). Finally, using a fluctuation sensitivity map, we establish which regions of the device are the most sensitive to the line-edge roughness and the metal grain granularity variability effects. The on-current of the device is strongly affected by any line-edge roughness taking place near the source-gate junction or by metal grains localised between the middle of the gate and the proximity of the gate-source junction. - Seoane N., Nagy D., Indalecio G., Espiñeira G., Kalna K., García-Loureiro A. - 10.3390/ma12152391
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