Benchmarking of Scaled InGaAs Implant-Free NanoMOSFETs
The potential performance of n-type implant-free (IF) III–V nanoMOSFETs with an In0.75Ga0.25As channel is studied using finite-element heterostructure Monte Carlo (MC) and parallel 3-D drift–diffusion (D–D) simulations. These devices, scaled to gate lengths of 30, 20, and 15 nm, are compared with the equivalent gate length In0.3Ga0.7As channel IF MOSFETs and with a state-of-the-art Si TriGate FinFET. The benchmarking study is based on careful calibration of the MC simulator against experimental transport data obtained from relevant δ-doped heterostructures with a high-κ gate dielectric. At 0.8-V supply voltage, the 30-nm gate length In0.75Ga0.25As channel IF III–V MOSFET is predicted to deliver a drive current of 2880 μA/μm and to have a subthreshold slope of 94.7 mV/dec compared with 2380 μA/μm for an equivalent gate length In0.3Ga0.7As channel IF MOSFET. When the In0.75Ga0.25As channel IF transistor is scaled to 20- and 15-nm gate lengths, the drive current increases to 3520 and 3605 μA/μm, featuring subthreshold slopes of 107.8 and 131.7 mV/dec, respectively. The threshold voltage variability induced by the discrete dopants in the δ-doped plane is studied using 3-D D–D simulations. The 30-, 20-, and 15-nm gate length In0.75Ga0.25As channel IF transistors exhibit threshold voltage standard deviations of 42, 58, and 61 mV, respectively, which are close to or lower than those observed in bulk Si MOSFETs with equivalent gate lengths.
keywords: InGaAs MOSFETs, Monte Carlo (MC) simulations, performance, thin-body architecture, variability.