Fluctuation Sensitivity Map: A Novel Technique to Characterise and Predict Device Behaviour Under Metal Grain Work-Function Variability Effects
A new technique developed for the analysis of intrinsic sources of variability affecting the performance of semiconductor devices is presented. It is based on the creation of a fluctuation sensitivity map (FSM), which supplies spatial information about the source of variability affecting the device performance and reliability, providing useful advice in the development of fluctuation-resistant device architectures. We have applied the FSM to metal grain work-function variations (MGWVs), since they are one of the major contributors to device variability. This technique is computationally very efficient because, once the original FSM is created, it can be used to predict the MGWV for different metal gates or grain sizes (GSs). Two state-of-the-art devices were used as test-models: a 10.7-nm gate length Si FinFET and 10.4-nm gate length In0.53Ga0.47As FinFET. The cross-sectional shape (triangular, rectangular, or bullet), the metal used in the gate (TiN or WN), and the GS (10, 7, and 5 nm) have been used as test scenarios for this technique.
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Publication: Article
1624014949294
June 18, 2021
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A new technique developed for the analysis of intrinsic sources of variability affecting the performance of semiconductor devices is presented. It is based on the creation of a fluctuation sensitivity map (FSM), which supplies spatial information about the source of variability affecting the device performance and reliability, providing useful advice in the development of fluctuation-resistant device architectures. We have applied the FSM to metal grain work-function variations (MGWVs), since they are one of the major contributors to device variability. This technique is computationally very efficient because, once the original FSM is created, it can be used to predict the MGWV for different metal gates or grain sizes (GSs). Two state-of-the-art devices were used as test-models: a 10.7-nm gate length Si FinFET and 10.4-nm gate length In0.53Ga0.47As FinFET. The cross-sectional shape (triangular, rectangular, or bullet), the metal used in the gate (TiN or WN), and the GS (10, 7, and 5 nm) have been used as test scenarios for this technique. - Guillermo Indalecio ; Natalia Seoane ; Karol Kalna ; Antonio J. García-Loureiro - 10.1109/TED.2017.2670060
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