In this paper, a parallel hardware implementation to accelerate the computation of the minimum embedding dimension is presented. The estimation of the minimum embedding dimension is a time-consuming task necessary to start the non-linear analysis of biomedical signals. The design presented has as main goals maximum performance and reconfigurability. The design process is explained, giving details on the decisions taken to achieve massive parallelization, as well as the methodology used to reduce hardware usage while keeping a high mathematical accuracy. The results yield that hardware acceleration achieves a speedup of three orders of magnitude in comparison to a purely software approach.