Highly Parallel Image Processing on a Massively Parallel Processor Array

During the last decades, semiconductors technology has steadily followed Moore's law, doubling the number of transistors per chip every 18/24 months. Microprocessors performance has grown at a similar pace by using those transistors to implement larger caches, deeper pipelines, wider superscalar paths and better branch prediction. However, this trend has been challenged in the last years due to the law of diminishing returns and immoderate power dissipation. Instead, multicore and manycore processors are the new wave of computing, o®ering higher performance by using large numbers of simple processors. In this paper, we describe the implementation of 2 applications into an Ambric massively parallel processor array. Processors are seen as logic blocks that are combined to build higher hierarchy blocks and, eventually, a complete system. An evaluation of performance and design e®ort is provided, showing that massive parallel processor arrays may challenges FPGAs in some applications.