This paper introduces a CMOS vision sensor chip for Gaussian pyramid extraction. The Gaussian pyramid provides computer vision algorithms with scale invariance, which permits
to have the same response regardless the distance of the scene to the camera. The chip is conceived as the mapping of an architecture for vertical technologies onto standard 0.18 μm
CMOS technology. It comprises 176 × 120 photosensing elements arranged in 88 × 60 processing elements (PEs). The Gaussian pyramid is generated with a double-Euler switched-capacitor network. Every processing element comprises four photodiodes, four MiM capacitors, one 8-bit single-slope Analog to Digital Converter (ADC) and one Correlated Double Sampling (CDS) circuit, occupying 44 × 44 μm2 . The paper assesses the accuracy of the Gaussian pyramid with metrics from the domain of visual tracking, with error levels below 2% full scale output (FSO) and an energy cost of 26.5 nJ/px at 2.64 Mpx/s, outperforming conventional solutions of imager and microprocessor unit (MPU).
Keywords: Gaussian Pyramid, SIFT, feature detectors, CMOS Vision Sensors