Thesis 1606
Author/s
  • Edoardo Emilio Coronado Barrientos
Read Center
  • CiTIUS
Doctoral Program
  • Doutoramento en Investigación en tecnoloxías da información

Parallelization and Optimization of Iterative Solvers On High Performance Architectures

The main objective of this thesis is to develop an optimal sparse matrix storage format and implement efficient computing kernels that accelerate the execution of the sparse matrix vector (SpMV) product on modern computer architectures. The SpMV product is an essential building brick for a myriad of numerical application codes, especially for iterative solvers and numerical simulators. Improving the performance of the SpMV product is of special interest for researchers, because it is the major bottleneck for codes where it is required. Optimizing this product on modern computer architectures requires knowledge of parallel programing paradigms, efficient parallel algorithms and a basic idea of the device architecture being targeted.
Keywords: High Performance Computing, Parallelization, Sparse Matrix Vector Product
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