Experimental analysis of CMOS short-channel gate enclosed transistors
The outstanding benefits of standard deep submicron CMOS technologies for the design of radiation tolerant devices can be further exploited by means of the use of special layout styles, such as the gate-enclosed transistors. This work constitutes a study of the impact of technology downscaling on the performance of this type of devices, particularly the threshold voltage roll-off due to short-channel effects and the drain-induced barrier lowering. Theoretical predictions have been validated with experimental data in a commercial 0.18μm CMOS process.
Palabras clave:
Publicación: Congreso
1624015012371
18 de xuño de 2021
/research/publications/experimental-analysis-of-cmos-short-channel-gate-enclosed-transistors
The outstanding benefits of standard deep submicron CMOS technologies for the design of radiation tolerant devices can be further exploited by means of the use of special layout styles, such as the gate-enclosed transistors. This work constitutes a study of the impact of technology downscaling on the performance of this type of devices, particularly the threshold voltage roll-off due to short-channel effects and the drain-induced barrier lowering. Theoretical predictions have been validated with experimental data in a commercial 0.18μm CMOS process. - P. López, B. Blanco-Filgueira, D. Cabello and J. Hauer
publications_gl