3DSVTUNANO: Scaling and variability of 3D tunneling field effect transistor nanowires using Si, Ge and III-V materials

Tunnel field-effect transistors (TFETs) are being investigated as potential candidates to replace conventional MOSFETs for ultra-low power applications due to their reduced sub-threshold slope and their steep-switching features that make possible to achieve aggressive scaling of the power supply voltage.

However, a challenge associated with these devices is their poor performance and low on-state current. In order to achieve high tunneling probabilities the use of heterojunctions and new architectures, such as gate-all-around nanowire (NW) structures is beneficial.

In this project, we will investigate an initial NW TFET device architecture following the designs provided by the recently published data. After that, different combinations of materials composing the channel, drain and the source of the device will be examined and the optimum architecture will be scaled down to other technological nodes in order to assess the performance and scalability. The modelling of these devices cannot be done without three-dimensional simulations. For this reason, we will use 3D geometry device simulation tools with atomistic resolution such as Finite Element quantum-corrected Drift-Diffusion and Monte Carlo simulations.


1. Three-dimensional modelling of nanowire tunnel field-effect transistors using the Drift-Diffusion and Monte Carlo methods

2. Study of the influence of different sources of variability on the performance of nanowire tunnel field-effect transistors

3. Optimisation of numerical algorithms, portability to new computational infrastructures and development of tools for the efficient handling of simulation data