CMOS Vision Sensor for Background Subtraction

Background subtraction is one of the first steps in many video processing algorithms. Thus, a real-time processing with low power consumption is convenient for different applications where power hungry devices with high computational capabilities can not be deployed. This work presents the design of a 24x56 pixel proof-of-concept 0.18 um standard CMOS vision sensor chip implementing the foreground detection algorithm Hardware Oriented Pixel Based Adaptive Segmenter (HO-PBAS) on the focal plane. Simulation results show a maximum processing speed of 2000 fps with a figure of merit of 1.3 uW/pixel at 60 fps and a pixel pitch of 47 um in a four pixels per processing element configuration.

keywords: CMOS vision sensor, focal plane, foreground detection, HO-PBAS