Feature detection and matching on an SIMD/MIMD hybrid embedded processor
This work presents the implementation of a feature detection and matching algorithm on an innovative SIMD/MIMD dynamically-reconfigurable architecture intended for high-performance embedded vision systems. An FPGA-based system-on-chip with a 128-unit coprocessor running at 150MHz is able to locate a target in 320 × 240 px images in less than 1 ms. It is also shown how to map the algorithms to speed-up the processing taking advantage of the different available computation modes.
keywords: Feature detection, matching, computer vision, SIMD/MIMD reconfigurable architectures, VHDL, FPGA