Congress 1167
  • D. García-Lesta; V. M. Brea; P. López; D. Cabello
  • 2018 IEEE International Symposium on Circuits and Systems. Florencia, Italia. 2018
Research Areas

Impact of Analog Memories Non-Idealities on the Performance of Foreground Detection Algorithms

The high number of memory accesses in background subtraction algorithms constraints the choice of the memory topology of an analog implementation of a hardware-oriented version of the well-known PBAS algorithm (HO-PBAS). As the first step towards the implementation of a CMOS vision chip with per-pixel processing to run the HO-PBAS, this work assesses the impact of the circuit non-idealities of the three main analog memory topologies into the segmentation result on the CDNET database.
Keywords: Topology, Capacitors, Analog memory, Degradation, Buffer storage, Vision sensors, Heuristic algorithms
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