Offset-Compensated Comparator with Full-Input Range in 150nm FDSOI CMOS-3D Technology
This paper addresses an offset-compensated comparator with full-input range in the 150nm FDSOI CMOS-3D technology from MIT- Lincoln Laboratory. The comparator discussed here makes part of a vision system. Its architecture is that of a self-biased inverter with dynamic offset correction. At simulation level, the comparator can reach a resolution of 0.75mV in an area of approximately 220μm2 with a time response of less than 200ns and a static power dissipation of 1.125μW.
keywords: Comparator, offset-compensated, CMOS-3D, FDSOI, In-pixel ADC
Publication: Congress
1624015013424
June 18, 2021
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This paper addresses an offset-compensated comparator with full-input range in the 150nm FDSOI CMOS-3D technology from MIT- Lincoln Laboratory. The comparator discussed here makes part of a vision system. Its architecture is that of a self-biased inverter with dynamic offset correction. At simulation level, the comparator can reach a resolution of 0.75mV in an area of approximately 220μm2 with a time response of less than 200ns and a static power dissipation of 1.125μW. - M. Suárez-Cambre, V. M. Brea, C. Domínguez-Matas, R. Carmona , G. Liñán, A. Rodríguez-Vázquez - 10.1109/LASCAS.2010.7410254
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