Simplification and Hardware Implementation of the Feature Descriptor Vector Calculation in the SIFT Algorithm
This paper proposes a hardware implementation to speed up the calculation of the feature descriptor vector in the Scale-Invariant Feature Transform (SIFT) algorithm. The proposed architecture, which improves conventional solutions based on embedded processors or other hardware/software co-designs, computes a feature descriptor vector of 27 elements from a keypoint neighborhood of 15x15 pixels. This process comprises several steps, including complex operations such as vector normalization operations. The paper compares two different implementations: one being time-optimized and the other memory-optimized. Both approaches require 649 and 874 clock cycles respectively for a single feature vector calculation (6.49 μs and 8.74 μs for a 100 MHz FPGA).
keywords: VHDL Scale Invariant Feature Transform (SIFT) FPGA
Publication: Congress
1624015027617
June 18, 2021
/research/publications/simplification-and-hardware-implementation-of-the-feature-descriptor-vector-calculation-in-the-sift-algorithm
This paper proposes a hardware implementation to speed up the calculation of the feature descriptor vector in the Scale-Invariant Feature Transform (SIFT) algorithm. The proposed architecture, which improves conventional solutions based on embedded processors or other hardware/software co-designs, computes a feature descriptor vector of 27 elements from a keypoint neighborhood of 15x15 pixels. This process comprises several steps, including complex operations such as vector normalization operations. The paper compares two different implementations: one being time-optimized and the other memory-optimized. Both approaches require 649 and 874 clock cycles respectively for a single feature vector calculation (6.49 μs and 8.74 μs for a 100 MHz FPGA). - Pablo Leyva, Gines Domenech-Asensi, Javier Garrigos, Julio Illade-Quinteiro, Victor Brea, Paula Lopez and Diego Cabello - 10.1109/FPL.2014.6927409
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