Scale- and Rotation-Invariant Feature Detectors on CMOS-3D Technology for Low-Power Vision Systems
The main goal in this project is to explore scale-, affine- and rotation-invariant feature detectors and their mapping onto CMOS-3D technologies. This project starts the way to future low-power stand-alone vision systems, which in turn could be used in: 1) embedded systems, where compact, light, low-power and high-performance platforms are needed, and/or 2) in distributed systems as wireless sensor networks, and particularly vision sensor networks, where low power consumption is a must.
Objectives
- Survey and study of SIFT and SURF algorithms
- Software with the incorporation of hardware errors
- Definition of the CMOS-3D architecture
- Modeling and characterization of the sensing plane
- Hardware implementation of the low-level tasks
- Hardware implementation of the high-level tasks
- PCB and testing of the resultant chip
Project
/research/projects/detectores-de-propiedades-invariantes-a-cambios-de-escala-e-rotacions-en-tecnoloxias-cmos-3d-para-sistemas-de-vision-de-baixo-consumo-de-potencia
<p>The main goal in this project is to explore scale-, affine- and rotation-invariant feature detectors and their mapping onto CMOS-3D technologies. This project starts the way to future low-power stand-alone vision systems, which in turn could be used in: 1) embedded systems, where compact, light, low-power and high-performance platforms are needed, and/or 2) in distributed systems as wireless sensor networks, and particularly vision sensor networks, where low power consumption is a must.</p>The main goal in this project is to explore scale-, affine- and rotation-invariant feature detectors and their mapping onto CMOS-3D technologies.<ol><li>Survey and study of SIFT and SURF algorithms</li><li>Software with the incorporation of hardware errors</li><li>Definition of the CMOS-3D architecture</li><li>Modeling and characterization of the sensing plane</li><li>Hardware implementation of the low-level tasks</li><li>Hardware implementation of the high-level tasks</li><li>PCB and testing of the resultant chip</li></ol> - Víctor Manuel Brea Sánchez - Paula López Martínez
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