HSHPC: Hardware and Software Support for High Performance Computing

Performance and programmability improvement of HPC systems, Software tools for HPC and Grid facilities, Performance improvement for multimedia applications and general purpose processors


The objectives of this project are a continuation of the results obtained during the development of the project TIN2004-07797-CO2. Taking these results as our starting point, we will deal with new objectives, some of them oriented to solve the new challenges that will arise with the forthcoming installation of the Finisterrae supercomputer at CESGA (Galician Supercomputing Center) in 2007. Finisterrae is a large constellation architecture composed of 142 shared memory nodes with 16 cores of Itanium processors plus other three ccNUMA nodes with 64, 64 and 128 cores (i.e, more than 2500 processors and 19.000 GB of memory). The objectives are organised into three main areas:

  1. Performance and programmability improvement of HPC systems. The main concern of this area is to improve the functionality of HPC systems, with special focus on irregular codes. We will consider irregular codes whose data accesses are ruled by indirection arrays or pointers and we will explore two approaches to deal with their complexity: analytical modelling, and runtime solutions such as inspector/executor. Both approaches require compiler support for analyzing these complex codes. This support will be provided by XARK, a compiler framework, developed at the UDC, for the automatic recognition of a comprehensive set of computational kernels. Moreover, we will tackle the improvement of the programmability of HPC systems (particularly constellation architectures, which mix the properties of shared memory and distributed memory systems) by developing optimized PGAS libraries to cover frequent computational kernels of parallel applications poorly supported by the language, ie. irregular computational kernels.
  2. Software tools for HPC and Grid facilities. First, the AdCIM middleware for system management (developed as part of the previous TIN2004 project) will be adapted to the new requirements of the Finisterrae supercomputer, and will be extended to be integrated in a Grid infrastructure. Second, the CPPC checkpointing tool (also part of the previous project) will be tuned to provide fault tolerance to applications executed on Finisterrae. A Globus service will also be developed to manage transparently the execution of fault tolerant applications on a Grid environment. The third goal deals with the understanding and characterization of the performance of Grid applications, as well as for the accurate simulation of Grid systems to reproduce real executions; then a tool for extracting guidelines for execution optimization on Grid facilities will be developed.
  3. Performance improvement for multimedia applications and general purpose processors: Design of new functional units and architectures for video compression, and new video compression algorithms and its implementation on general purpose multicore processors, high performance DSPs and FPGAs. Additionally, it includes the design of functional units to improve the performance of general purpose processors. In latter case we will focus on the most expensive basic floating-point operations, division and square root, and on decimal arithmetic.