TACLe: Timing Analysis on Code-Level
Embedded systems increasingly permeate our daily lives. Many of those systems are business- or safety-critical, with strict timing requirements. Code-level timing analysis (used to analyze software running on some given hardware w.r.t. its timing properties) is an indispensable technique for ascertaining whether or not these requirements are met. However, recent developments in hardware, especially multi-core processors, and in software organization render analysis increasingly more difficult, thus challenging the evolution of timing analysis techniques.
New principles for building "timing-compostable" embedded systems are needed in order to make timing analysis tractable in the future. This requires improved contacts within the timing analysis community, as well as with related communities dealing with other forms of analysis such as model-checking and type-inference, and with computer architectures and compilers.
The CiTIUS partipates in this action in the Workpackage 1, that deal with the analysis of timing models for multi-cores and with the timing composability.
Objectives
The goal of this COST Action is to gather these forces in order to develop industrial-strength code-level timing analysis techniques for future-generation embedded systems.
Project
/research/projects/timing-analysis-on-code-level
<p>Embedded systems increasingly permeate our daily lives. Many of those systems are business- or safety-critical, with strict timing requirements. Code-level timing analysis (used to analyze software running on some given hardware w.r.t. its timing properties) is an indispensable technique for ascertaining whether or not these requirements are met. However, recent developments in hardware, especially multi-core processors, and in software organization render analysis increasingly more difficult, thus challenging the evolution of timing analysis techniques.</p> <p>New principles for building "timing-compostable" embedded systems are needed in order to make timing analysis tractable in the future. This requires improved contacts within the timing analysis community, as well as with related communities dealing with other forms of analysis such as model-checking and type-inference, and with computer architectures and compilers.</p> <p>The CiTIUS partipates in this action in the Workpackage 1, that deal with the analysis of timing models for multi-cores and with the timing composability.</p><p>The goal of this COST Action is to gather these forces in order to develop industrial-strength code-level timing analysis techniques for future-generation embedded systems.</p> - Francisco Fernández Rivera - José Carlos Cabaleiro Domínguez, Tomás Fernández Pena, Juan Carlos Pichel Campos
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