Analyzing the Execution of Sparse Matrix-Vector Product on the Finisterrae SMP-NUMA System
In this paper, the sparse matrix-vector product (SpMV) is evaluated on the FINISTERRAE SMP-NUMA supercomputer. Its architecture particularities make the tuning of SpMV especially relevant due to the significant impact on the performance. First, we have estimated the influence of data and thread allocation. Moreover, because of the indirect and irregular memory access patterns of SpMV, we have also studied the influence of the memory hierarchy in the performance. According to the behavior observed in the study, a set of optimizations specially tuned for FINISTERRAE were successfully applied to SpMV. Noticeable improvements are obtained in comparison with the SpMV naïve implementation.
keywords: Sparse matrix, NUMA, Thread affinity, Memory hierarchy