Live Demonstration: A Mixed-Mode Signal CMOS Chip for Hyperdimensional Computing
This live demonstration shows a mixed-signal design in 180 nm CMOS technology that runs hyperdimensional computing (HDC) on binary hypervectors with up to 8,192 components. The chip comprises 64 × 128 processing elements (PE) arranged in a 2D mesh with direct connection to their first neighbors. PEs include a 1-bit ALU with a 16 6T-SRAM bank to execute HDC primitives. Hypervector classification is performed through the Hamming distance with current sources in every PE globally connected to an analog computing unit laid down outside the PE array. The overall approach results in tens of nJ of power consumption in inference, which is competitive with state-of-the-art solutions.
keywords: Hyperdimensional computing, Standard CMOS Technology, Low-power
Publication: Congress
1729596912695
October 22, 2024
/research/publications/live-demonstration-a-mixed-mode-signal-cmos-chip-for-hyperdimensional-computing
This live demonstration shows a mixed-signal design in 180 nm CMOS technology that runs hyperdimensional computing (HDC) on binary hypervectors with up to 8,192 components. The chip comprises 64 × 128 processing elements (PE) arranged in a 2D mesh with direct connection to their first neighbors. PEs include a 1-bit ALU with a 16 6T-SRAM bank to execute HDC primitives. Hypervector classification is performed through the Hamming distance with current sources in every PE globally connected to an analog computing unit laid down outside the PE array. The overall approach results in tens of nJ of power consumption in inference, which is competitive with state-of-the-art solutions. - García-Lesta D., Pardo F., Pereira-Rial Ó., Brea V.M., López P., Cabello D. - 10.1109/ISCAS58744.2024.10558160
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