Diego Cabello Ferrer

1.88 nA Quiescent Current Capacitor-Less LDO with Adaptive Biasing Based on a SSF Absolute Voltage Difference Meter
CMOS Vision Sensor for Background Subtraction
On-Chip Solar Energy Harvester and PMU with Cold Start-Up and Regulated Output Voltage for Biomedical Applications
Design methodology of a 0.7 V, 64.5 pW @ 36°C, 1830 μm² Subthreshold Voltage Reference for Implantable Devices
Ultralow power voltage reference circuit for implantable devices in standard CMOS technology
Time-of-Flight Pixel with Homodyne Phase Demodulation in Standard CMOS Technology
On-Chip Solar Cell and PMU on the Same Substrate with Cold Start-Up from nW and 80 dB of Input Power Range for Biomedical Applications
Micro-Energy Harvesting System including a PMU and a Solar Cell on the same Substrate with Cold Start-Up from 2.38 nW and Input Power Range up to 10μW using Continuous MPPT
In‐pixel analog memories for a pixel‐based background subtraction algorithm on CMOS vision sensors
Live Demonstration: Light Energy Harvesting System with an On-Chip Solar Cell and Cold Start-Up
Shannon Entropy as Background Dynamics Estimator In Foreground Detector Algorithms
Impact of Analog Memories Non-Idealities on the Performance of Foreground Detection Algorithms
Pulsed Time-of-Flight Pixel with on-Chip 20 klux Background Light Suppression in Standard CMOS Technology
Wireless Sensor Network with Perpetual Motes for Terrestrial Snail Activity Monitoring
Dynamic Model of Switched-Capacitor DC-DC Converters in the Slow-Switching Limit including Charge Reusing
Effect of Temporal and Spatial Noise on the Performance of Hardware Oriented Background Extraction Algorithms
Low Power CMOS Vision Sensor for Gaussian Pyramid Extraction
Dynamic joint model of capacitive charge pumps and on-chip photovoltaic cells for CMOS micro-energy harvesting
Real time architectures for the Scale Invariant Feature Transform algorithm
Live Demonstration: Wireless Sensor Network For Snail Pest Detection
Dynamic Model of On-Chip Inverting Capacitive Charge Pumps with Charge Reusing
Time-of-Flight Chip in Standard CMOS Technology with In-Pixel Adaptive Number of Accumulations
Design for Maximum Power Transfer Efficiency of Thermoelectric Generators using Mixed Mode Simulations
Image Feature Extraction Acceleration
Live Demonstration: Gaussian Pyramid Extraction with a CMOS Vision Sensor
Dark Current Optimization of 4-Transistor Topologies in Standard CMOS Technologies for Time-of-Flight Sensors
Capacitance-based Wireless Sensor Mote for Snail Pest Detection
Distance Measurement Error in Time-of-Flight Sensors Due to Shot Noise
Four-transistor pinned photodiodes in standard CMOS technologies for time-of-flight sensors
Wireless Sensor Mote for Snail Pest Detection
A 26.5 nJ/px 2.64 Mpx/s CMOS Vision Sensor for Gaussian Pyramid Extraction
Simplification and Hardware Implementation of the Feature Descriptor Vector Calculation in the SIFT Algorithm
The Dickson Charge Pump as Voltage Booster for Light Energy Harvesting on CMOS Vision Chips
Custom Design of Pinned Photodiodes in Standard CMOS Technologies for Time-of-Flight Sensors
Gaussian Pyramid Extraction with a CMOS Vision Sensor
Dark Current in Standard CMOS Pinned Photodiodes for Time-of-Flight Sensors
Split and Shift Methodology on Cellular Processor Arrays: Area Saving versus Time Penalty
CMOS-3D Smart Imager Architectures for Feature Detection
Design of a smart camera system on a single chip in 3D integrated circuit technology
GPU-based infrared thermography for NDE of minefields
In-Pixel Generation of Gaussian Pyramid Images by Block Reusing in 3D-CMOS
Scale- and rotation-invariant feature detectors on Cellular Processor Arrays
Handsheet for Full-Custom Circuit Design
A 2D model for radiation-hard CMOS annular transistors
Experimental analysis of CMOS short-channel gate enclosed transistors
Efficient software-hardware 3D heat equation solver with applications on the non-destructive evaluation of minefields
A study of CMOS radiation tolerant transistors using Green functions
Non-destructive soil inspection using an efficient 3D software-hardware heat equation solver
Analytical model of short-channel gate enclosed transistors using Green functions
A dc I-V model for short-channel polygonal enclosed-layout transistors
Enclosed layout transistors in saturation
Modeling and simulation of CMOS APS
CNN Technology for Spatiotemporal Signal Processing
Efficient software-hardware 3D heat equation solver with applications on the non-destructive evaluation of minefields
Single Instruction Multiple Data and Cellular Non-linear Networks as Fine-Grained Parallel Solutions for Early Vision on FPGAs
Sensitivity of photodiode-based CMOS APS in 0.18um technology: peripheral collection and optimum dimension
Discrete Time Cellular Non-linear Networks Implementation over FPGA
Bottom collection of photodiode-based CMOS APS
Template-Oriented Hardware Design based on Shape Analysis of 2D CNN Operators in CNN Template Libraries and Applications
DT-CNN emulator: 3D heat equation solver with applications on the non-destructive soil inspection
FPGA-based hardware accelerator of the heat equation with applications on infrared thermography
Proceedings of the IEEE International Workshop on Cellular Neural Networks and their Applications: Preface
Soft-Hard 3D FD-TD solver for non destructive evaluation
Verification of Split&Shift Techniques for CNN Hardware Reduction
Improved Analytical I-V Model for polygonal-shape enclosed layout transistors
Relating Cellular Non-linear Networks to Threshold Logic and Single Instruction Multiple Data Computing Models
CNN Implementation of Spin Filters for Electronic Speckle Pattern Interferometry Applications
Area and Time Efficient Cellular Non-linear Networks
Diseño de sensores ópticos CMOS y dispositivos electrónicos para procesado de imágenes en tiempo real